Aim

To Implement a simplified but functional NES emulator on FPGA that demonstrates:

• Ricoh 2A03 CPU instruction execution (subset of 151 opcodes)
• Basic PPU tile rendering and sprite evaluation
• 64KB memory mapping with internal RAM and cartridge ROM
• VGA video output for static frame display
• GPIO controller input handling

Introduction

The Nintendo Entertainment System (NES), launched in 1985, revolutionized gaming with its 8-bit architecture featuring Ricoh 2A03 CPU (1.79MHz 6502 derivative), Ricoh 2C02 PPU, 2KB RAM, and cartridge-based storage. This FPGA project recreates these core components to study retro hardware behavior, digital system design, clock domains, and modular datapath implementation.

The project targets the Digilent Nexys A7 FPGA board and uses Verilog HDL for synthesizable RTL design. It exposes structural and timing challenges of real hardware realization, including finite-state control, memory mapping, and CPU-PPU synchronization.

Literature Survey and Technologies Used

Key Prior Works

• MIT 6.111 (2004): Downey et al. Complete NES design with VGA/audio on Cyclone FPGAs
• University of Florida (2012): Eric King implemented full VHDL NES system
• Carnegie Mellon ECE500 (2019): Team A8 achieved <1% frame difference vs reference emulation
• MIT 6.111 (2019): Klahn's NES hardware emulation with cycle-accurate 6502

Technologies Used

METHODOLOGY

1. CPU Implementation (Ricoh 2A03)

4-Stage Pipeline:

IDLE → FETCH → DECODE → EXECUTE → WRITEBACK → IDLE

FETCH: PC++ and read opcode byte from memory[PC]

DECODE: ROM table lookup for addressing mode (Zero Page, Absolute, Indexed, Indirect)

EXECUTE: ALU operation or branch calculation

WRITEBACK: Register/memory update + flags (N,Z,C,V)

Clocking: 100MHz FPGA ÷ 56 = 1.79MHz NES CPU speed
Opcodes: 48/151 implemented (LOAD/STORE, BRANCH, ARITHMETIC)
Timing: Variable 2-7 cycles per instruction matching original 6502

2. PPU Implementation (Ricoh 2C02)

Memory Map:

• Nametable: $2000-$2FFF (32×30 tiles, mirrored)
• Pattern Tables: $0000-$1FFF (8×8 tiles, 2BPP → 4 colors)
• Palette RAM: $3F00-$3F1F (32 bytes, 52 colors)
• OAM: $0200-$02FF (64 sprites × 4 bytes)

Scanline Processing (341 PPU clocks/line):

1. Fetch nametable tile indices
2. Pattern fetch + 2BPP → pixel colors
3. Sprite evaluation: 64 sprites → top 8 per scanline
4. BG + sprite pixel blending (priority-based)
5. VGA RGB565 output

3. Integration & Timing

Frame Flow:

1. CPU reset → $FFFC vector
2. PPU VBLANK clear
3. CPU main loop + sprite DMA ($4014)
4. PPU renders 240 visible scanlines
5. VBLANK → NMI interrupt (lines 241-262)

Repeat @60Hz

Development Flow:

RTL Design → Simulation (Vivado) → Synthesis → Timing Analysis → Bitstream → Nexys A7

Results

Functional Achievements

• CPU: 48/151 opcodes, 11 addressing modes, 64KB memory mapping
• PPU: 256×240 NTSC rendering, 52-color palette, 8 sprites/scanline
• Video: Stable VGA output
• ROM Support: NROM mapper (Super Mario Bros.)
• Controller: GPIO 

Validation: Super Mario Bros. ROM renders static title screen frames with pixel-accurate graphics and stable 60Hz refresh.

Conclusions/Future Scope

Achievements

• Successfully recreated core NES functionality on Nexys A7 FPGA
• Achieved pixel-accurate rendering of commercial NES ROMs
• Demonstrated CPU-PPU synchronization and NTSC timing

Limitations

• Simplified mapper support (NROM only)
• Subset of CPU opcodes (48/151)
• No audio processing (APU)
• Functional accuracy prioritized over cycle-perfect timing

Future Enhancements

• Full mapper support 
• Complete 151-opcode CPU implementation
• APU audio synthesis and stereo output
• HDMI output 
• Cycle-accurate timing for commercial ROM compatibility

References/Links to GitHub Repo

• Downey, Kauppila, Myhre. The Design and Implementation of the Nintendo Entertainment System. MIT 6.111 Final Project Report, Fall 2004
• Klahn, D. NES Hardware Emulation Design Presentation. MIT 6.111 Project, Fall 2019
• King, Eric. FPGA NES Implementation. University of Florida Senior Design Project, 2012
• Team A8. NES Emulation on FPGA. Carnegie Mellon ECE500 Capstone, Spring 2019
• Copetti, Rodrigo. NES/Famicom Architecture: A Practical Analysis (2026). https://www.copetti.org/writings/consoles/nes/
• NESdev Wiki. NES Technical Reference. https://www.nesdev.org/NESDoc.pdf
• Ganyer, Jonathan. NES on FPGA Implementation. https://jonathanganyer.wordpress.com/nes-fpga/

GitHub Repository:
github.com/NITK-IEEE/NES-on-FPGA (Verilog sources, testbenches, bitstreams, documentation)