Gmeet Link : D12 : RegisterRail

Github Repo: Register Rail

Introduction

Modern embedded systems rely heavily on efficient digital signal acquisition, processing, communication, and reconstruction. In real-world systems such as oscilloscopes, sensor nodes, data acquisition systems, biomedical devices, and communication equipment, analog signals must be sampled, digitized, transmitted reliably, and reconstructed accurately.

RegisterRail demonstrates a complete end-to-end embedded signal processing and communication pipeline implemented entirely on an ARM Cortex-M based STM32 microcontroller using bare-metal programming. Unlike conventional approaches that depend on vendor abstraction libraries such as STM32 HAL or Arduino frameworks, this project directly manipulates peripheral registers through memory-mapped I/O, providing fine-grained control over the hardware and deeper understanding of embedded system internals.

The system captures one full period of an analog sine wave using the ADC, compresses the sampled data using delta encoding, transmits the compressed frame between two SPI peripherals on the same microcontroller, verifies data integrity using CRC16-CCITT error checking, reconstructs the waveform, and continuously replays the signal through the DAC using timer-driven interrupts.The project serves both as a practical engineering implementation and as a strong educational demonstration of low-level embedded system development.

Aim

The aim of this project is to design and implement a complete bare-metal embedded signal processing pipeline on an STM32 ARM Cortex-M microcontroller capable of:

• Sampling an analog signal using ADC
• Digitally compressing the acquired samples
• Transmitting the compressed data over SPI communication
• Detecting transmission errors using CRC16
• Reconstructing the original waveform from compressed data
• Replaying the waveform continuously using DAC output
• Demonstrating real-time interrupt-driven embedded programming
• Understanding the internal architecture and peripheral operation of ARM-based SoCs

The project also aims to strengthen practical understanding of:

• Register-level peripheral programming
• Interrupt-driven communication systems
• Real-time embedded software design
• Signal acquisition and reconstruction
• Digital communication reliability mechanisms
• Hardware-software interaction in microcontrollers

Technologies Used

Hardware Components

• STM32 Nucleo Development Board
• ARM Cortex-M Microcontroller
• Function Generator
• Oscilloscope
• Jumper Wires
• RC Low-Pass Filter Components
• DAC Output Circuit

Methodology

The RegisterRail Pipeline follows a sequential signal acquisition and reconstruction architecture consisting of multiple tightly coupled embedded subsystems.

1. System Initialization

All peripherals were initialized manually through direct register manipulation without using any hardware abstraction libraries.

The following peripherals were configured:

• GPIO
• ADC1
• SPI1 (Master)
• SPI2 (Slave)
• DAC
• TIM6
• EXTI Interrupts
• NVIC Interrupt Controller

Clock gating and peripheral enabling were handled through RCC registers.

This approach provided complete visibility into how the STM32 microcontroller internally configures and controls peripherals.

2. Button Trigger and State Machine

The blue push button connected to PC13 was configured as an external interrupt source using EXTI.

When the button is pressed:

• EXTI15_10 interrupt is triggered
• ISR updates the global state machine
• Main loop detects the state transition
• Sampling process begins

A lightweight finite state machine architecture was used to coordinate:

• Idle state
• Sampling state
• Transmission state
• Verification state
• Reconstruction state
• Replay state

This ensured organized real-time control flow without using an RTOS.

3. ADC Signal Sampling

The analog input signal was generated using a function generator:

• Frequency: 100 Hz
• Amplitude: 3V peak-to-peak
• DC Offset: 1.65V

The offset ensured the signal remained within the STM32 ADC input range of 0–3.3V.

ADC1 was configured for:

• 12-bit resolution
• Software-triggered conversions
• Single-channel input on PA0

Sampling frequency:

Sampling Rate = 30 kHz
Signal Frequency = 100 Hz
Samples per Sampling Rate = 30 kHz
Signal Frequency = 100 Hz
Samples per Period = 300Period = 300

Each sample was stored in:

adc_buffer[300]

This stage demonstrates practical implementation of the Nyquist sampling principle and discrete-time signal acquisition.

4. Delta Encoding Compression

Instead of transmitting all 300 raw 12-bit samples directly, delta encoding was used to reduce transmission size.

For a slowly varying sine wave sampled at high frequency, the difference between consecutive samples remains small.

Instead of storing:
- Absolute sample values

the system stores:
- Difference between adjacent samples
 

Frame structure:

Byte 0      : Header (0xAA)
Byte 1-2    : Initial absolute sample
Byte 3-301  : 299 signed 8-bit deltas
Byte 302-303: CRC16 checksum

This reduced transmission size significantly:

Raw Data  : 600 bytes
Compressed: 304 bytes

This stage demonstrates practical digital data compression techniques used in communication systems.

5. CRC16 Error Detection

To ensure reliable communication, CRC16-CCITT error detection was implemented.

Configuration:

Polynomial : 0x1021
Initial Value : 0xFFFF

The CRC was computed over:  Header + Seed + Delta Data 

and appended to the transmission frame.

On reception:

• CRC is recomputed
• Received CRC is compared
• Invalid frames are discarded

This demonstrates real-world communication integrity verification techniques used in industrial and networking systems.

6. SPI Communication

The project used:

- SPI1 as Master
- SPI2 as Slave

Both peripherals operated on the same STM32 board using jumper wire connections.

Connections:

PA5  → PB10   (SCK)
PA7  → PB15   (MOSI)
PA6  → PB14   (MISO)

Key architectural features:

• Interrupt-driven SPI communication
• Software slave management
• NVIC priority handling
• Overrun prevention
• Full-duplex serial transfer

The SPI slave interrupt was given higher priority than the SPI master interrupt to guarantee reliable reception.

This stage provided practical understanding of:

• Serial communication timing
• Hardware buffering
• Interrupt synchronization
• Peripheral interaction
• ARM NVIC behaviour

7. Signal Reconstruction

After successful reception:

•  CRC is verified
• Delta values are decoded
• Original waveform samples are reconstructed

Reconstruction formula:

output[0] = seed
output[i] = output[i-1] + delta[i-1]

Values were clamped between: 0 to 4095
 

The reconstructed signal was stored in:

dac_buffer[300]

This stage demonstrates practical digital signal reconstruction and discrete-time signal recovery.

8. DAC Replay Using TIM6

TIM6 was configured to generate periodic interrupts at: 30 kHz
 

Each interrupt:

• Writes one sample to DAC
• Advances playback index
• Wraps after 300 samples

The DAC continuously reproduced the captured waveform on PA4.

Observed output: 100.00139 Hz sine wave

The staircase approximation visible at high zoom levels demonstrated practical quantized signal reconstruction.

An RC low-pass filter could smooth the output into a near-continuous analog waveform.

Result obtained: 

Learning Outcomes

Through this project, the following concepts were learned and practically implemented:

Embedded Systems

• ARM Cortex-M internal architecture
• Peripheral interfacing
• Register-level programming
• Interrupt handling
• Real-time embedded design

Bare-Metal Programming

• Writing drivers without HAL
• Understanding peripheral registers
• Clock tree configuration
• Direct hardware manipulation
• Low-level debugging

Communication Systems

• SPI serial communication
• Master-slave synchronization
• Data framing
• Communication reliability

Signal Processing

• Sampling theorem
• Signal reconstruction
• Quantization effects
• Compression techniques
• DAC waveform synthesis

Systems Engineering

• Modular firmware design
• State machine architecture
• Error handling
• Timing analysis
• Hardware-software integration

Future Enhancements

The current implementation can be extended further in several ways:

DMA-Based Transfers

Using DMA for ADC, SPI, and DAC would reduce CPU overhead and improve efficiency.

Hardware CRC Peripheral

STM32 hardware CRC engine could accelerate checksum computation.

Real-Time Streaming

Instead of one-period capture, continuous streaming could be implemented.

Multi-Waveform Support

The system could support:

• Square waves
• Triangle waves
• Arbitrary waveform generation

Digital Filtering

Implementing FIR or IIR filters would improve reconstructed signal quality.

Wireless Communication

SPI transmission could be replaced with:

• RF modules
• Bluetooth
• Wi-Fi
• LoRa

for remote signal transmission.

RTOS Integration

A real-time operating system could be introduced for task scheduling and scalability.

Graphical Visualization

A UART or USB interface could stream captured samples to a PC for real-time plotting and analysis.

Conclusion

The RegisterRail Pipeline project successfully demonstrates a complete embedded digital signal acquisition and reconstruction system implemented entirely using bare-metal programming techniques on an STM32 ARM Cortex-M microcontroller.

The project combines low-level hardware control, digital communication, signal processing, data compression, and real-time interrupt-driven software architecture into a single integrated system.

By avoiding high-level abstraction libraries and directly interacting with hardware registers, the project provided deep practical understanding of:

• ARM microcontroller architecture
• Memory-mapped I/O
• Peripheral interfacing
• Real-time embedded systems
• Digital communication protocols
• Signal processing fundamentals

The successful reconstruction of the original analog waveform with highly accurate frequency reproduction validates both the hardware design and software architecture.

This project serves as a strong demonstration of practical embedded systems engineering and showcases how modern digital communication pipelines operate internally at the hardware-software boundary.

Mentors and Mentees details:

Mentors:                                                               Mentees:

Abhinav S Rao (241EC101)                                               Neo Anil Dodti, Nissim Bansal,

Abhishek Agrawal (241EC202)                                          Aman Tandon, Mahadevan SR,

Joseph Varghese (241EC125)                                           Sojal Chaudhari, Sriharsh Indarapu

Shouryadip Chakraborty (241EC152)                                Ishan Bhide